1. Field of the Invention
The present invention relates to a microcomputer which can read analog-to-digital converted results from an analog-to-digital (AD) converter built in the microcomputer.
2. Description of the Prior Art
Referring now to FIG. 29, there is illustrated a block diagram of a prior art microcomputer. In the figure, reference numeral 1 denotes an AD register disposed in an AD converter (see FIG. 30) for storing digital data which is an AD conversion result produced by the AD converter, which will be mentioned below, as a set of a plurality of data bits D0 to D4, 2 denotes a central processing unit (CPU) which is adapted to read the lowermost four data bits (i.e., a plurality of data bits D0 to D3) of digital data stored in the AD register 1 by furnishing an instruction signal c to read the lowermost four bits and, after that, read the uppermost data bit (i.e., data bit D4) of the digital data by furnishing an instruction signal ax to read the uppermost bit so as to identify the value of the digital data, 3 denotes a gate circuit for getting and furnishing the data bits D0 to D3 stored in the AD register 1 by way of a data bus 4 of the microcomputer in response to the lowermost four bits reading instruction signal c from the CPU 2, and.5 denotes a gate circuit for getting and furnishing the data bit D4 stored in the AD register 1 by way of the data bus 4 in response to the uppermost bit reading instruction signal ax from the CPU 2.
Referring next to FIG. 30, there is illustrated a block diagram showing the structure of the AD converter. In the figure, reference numeral 6 denotes a reference voltage input terminal through which a reference voltage ao can be applied, 7 denotes a ground voltage input terminal through which a ground voltage ap can be applied, 8 denotes an AD ladder resistor which can furnish a comparison voltage ar according to the reference voltage ao and a value stored in a successive comparison register 12, 9 denotes an analog input terminal through which an analog data aq to be analog-to-digital converted can be applied, 10 denotes a comparison circuit which compares the analog data aq with the comparison voltage ar to furnish a comparison result at, and 11 denotes an AD conversion control circuit which furnishes a comparison result signal au according to the comparison result at from the comparison circuit 10 so as to change the value stored in the successive comparison register 12. Thus, the value stored in the successive comparison register 12 is used for setting the comparison voltage ar.
When the AD converter begins its AD converting operation, "10000B" is written into the successive comparison register 12 as its initial value. In this case, the data bits D0 to D3 are "0" and the data bit D4 is "1". Then, the reference voltage ao of 3.2 V is applied to the reference voltage input terminal 6, and the ground voltage of 0 V is applied to the ground voltage input terminal 7. When the microcomputer is thus set to such a state initially, the AD ladder resistor 8 calculates the comparison voltage ar by substituting the reference voltage ao and the value stored in the successive comparison register 12 into the following expression so as to apply the comparison voltage ar to the comparison circuit 10. EQU Comparison voltage ar=(the reference voltage ao/32).times.(the value in the successive comparison register 12)-(the reference voltage ao/64)(1)
Accordingly, the value of the comparison voltage ar is 1.55 V under the above initial condition.
When the AD ladder resistor 8 furnishes the comparison voltage ar, the comparison circuit 10 compares the analog data aq with the comparison voltage ar. For example, when the analog data aq is 1.0 V, the comparison circuit 10 furnishes the comparison result at showing that the analog data aq is lower than the comparison voltage ar (i.e., 1.55 V) to the AD conversion control circuit 11.
When the AD conversion control circuit 11 receives the comparison result at, it furnishes the comparison result signal au requesting reduction in the comparison voltage ar to the successive comparison register 12. When the successive comparison register 12 receives the comparison result signal au, it replaces the value stored therein by "01000B". That is, the data bit D4 is changed from "1" to "0" and the data bit D3 is changed from "0" to "1", so that the value is reduced to the half.
When the value of the successive comparison register 12 is thus changed, the AD ladder resistor 8 calculates the comparison voltage ar by substituting the reference voltage ao and the updated value stored in the successive comparison register 12 into the above expression (1) so as to apply the comparison voltage ar to the comparison circuit 10. Under this condition, the comparison voltage ar becomes 0.75 V.
When the AD ladder resistor 8 furnishes the comparison voltage ar, the comparison circuit 10 compares the analog data aq with the comparison voltage ar. For example, when the analog data aq is 1.0 V, since the analog data aq is larger than the comparison voltage ar (i.e., 0.75 V), the comparison circuit 10 furnishes the comparison result at showing that the analog data aq is larger than the comparison voltage ar to the AD conversion control circuit 11. When the AD conversion control circuit 11 receives the comparison result at, it furnishes the comparison result signal au requesting an increase in the comparison voltage ar to the successive comparison register 12. When the successive comparison register 12 receives the comparison result signal au, it replaces the value stored therein by "01100B". That is, the data bits D4 and D3 are fixed so as to keep their current values, and the bit data D2 is changed from "0" to "1".
The above-mentioned operation is repeated until the data bits D4 to D0 are fixed; since the number of bits of the successive register 12 is five, the values of the bit data D4 to D0 can be fixed by repeating the above operation five times. When the respective values of the bit data D4 to D0 are fixed, the AD conversion control circuit 11 transfers the value stored in the successive comparison register 12 as the AD conversion result to the AD register 1. Thus, the AD conversion is completed. Then, the AD conversion control circuit 11 furnishes the AD conversion end signal ac showing that the AD conversion has been completed to the CPU 2.
Referring next to FIG. 31, there is illustrated a flow diagram showing the operation of the prior art microcomputer. When the AD conversion control circuit 11 furnishes the AD conversion end signal ac, the CPU 2, in step ST1, furnishes the lowermost four bits reading instruction signal c to the gate circuit 3. As a result, the gate circuit 3 makes a transition from the nonconducting state to the conducting state in step ST2, and therefore the lowermost four data bits (i.e., data bits D0 to D3) stored in the AD register 1 are delivered by way of the data bus 4. Accordingly, the CPU 2, in step ST3, reads the data bits D0 to D3 from the data bus 4.
Then, when the CPU 2 has completed reading these data bits D0 to D3, it furnishes the uppermost bit reading instruction signal ax to the gate circuit 5 in step ST4. As a result, the gate circuit 5 makes a transition from the nonconducting state to the conducting state in step ST5, and therefore the uppermost data bit (i.e., data bit D4) stored in the AD register 1 is delivered by way of the data bus 4. Accordingly, the CPU 2, in step ST6, reads the data bit D4 from the data bus 4.
When the CPU 2 has completed reading the data bits D0 to D4, it can identify the value of the digital data obtained by the AD conversion from the bit data D0 to D4 in step ST7. The series of processes are thus complete.
Since the prior art microcomputer is constructed as mentioned above, in the case where the number of the data bits D0 to D4 stored in the AD register 1 exceeds the number of bits (e.g., four bits in the prior art microcomputer shown in FIG. 29) that can be read at one time by the CPU 2, the CPU 2 cannot read the respective values of the data bits D0 to D4 stored in the AD register 1 at one time. Therefore, a problem with the prior art microcomputer is that it cannot promptly identify the value of digital data obtained by AD conversion since it has to read the data by dividing the reading process into at least two successive parts.